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very low power cmos sram 256k x 8 bit bs62lv2006 r0201 - b s62lv2006 revision 1.3 may. 2006 1 pb-free and green package materials are compliant to rohs n features ? wide v cc operation voltage : 2.4v ~ 5.5v ? very low power consumption : v cc = 3.0v operation current : 23ma (max.) at 55ns 2ma (max.) at 1mhz standby current : 0.1ua (typ.) at 25 o c v cc = 5.0v operation current : 55ma (max.) at 55ns 10ma (max.) at 1mhz standby current : 0.6ua (typ.) at 25 o c ? high speed access time : -55 55ns (max.) at v cc : 3.0~5.5v -70 70ns (max.) at v cc : 2.7~5.5v ? automatic power down when chip is deselected ? easy expansion with ce2, ce1 and oe options ? three state outputs and ttl compatible ? fully static operation ? data retention supply voltage as low as 1.5v n description the bs62lv2006 is a high performance, very low power cmos static random access memory organized as 262,144 by 8 bits and operates form a wide range of 2.4v to 5.5v supply voltage. advanced cmos technology and circuit techniques provide both high speed and low power features with typical cmos standby current of 0.1ua at 3.0v/25 o c and maximum access time of 55ns at 3.0v/85 o c. easy memory expansion is provided by an active low chip enable (ce1), an active high chip enable (ce2), and active low output enable (oe) and three-state output drivers. the bs62lv2006 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. the bs62lv2006 is available in dice form, jedec standard 32 pin 450mil plastic sop, 8mmx13.4mm stsop, 8mmx20mm tsop and 36-ball bga package. n power consumption power dissipation standby (i ccsb1 , max) operating (i cc , max) v cc =5v v cc =3v product family operating temperature v cc =5.0v v cc =3.0v 1mhz 10mhz f max. 1mhz 10mhz f max. pkg type bs62lv2006dc dice bs62lv2006hc bga-36-0608 bs62lv2006sc sop-32 bs62lv2006stc stsop-32 bs62lv2006tc commercial +0 o c to +70 o c 6.0ua 0.7ua 9ma 29ma 53ma 1.5ma 9ma 22ma tsop-32 bs62lv2006hi bga-36-0608 bs62lv2006si sop-32 bs62lv2006sti stsop-32 bs62lv2006ti industrial -40 o c to +85 o c 20ua 2.0ua 10ma 30ma 55ma 2ma 10ma 23ma tsop-32 n pin configurations n block diagram brilliance semiconductor, inc. reserves the right to change products and specifications without notice. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a17 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd vcc a15 ce2 we a13 a8 a9 a11 oe a10 ce1 dq7 dq6 dq5 dq4 dq3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bs62lv2006s c bs62lv2006si ? oe a10 ce1 dq7 dq6 dq5 dq4 dq3 gnd dq2 dq1 dq0 a0 a1 a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a11 a9 a8 a13 we ce2 a15 vcc a17 a16 a14 a12 a7 a6 a5 a4 ? bs62lv2006t c bs62lv2006ti bs62lv2006stc bs62lv2006sti 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 address input buffer row decoder memory array 1024 x 2048 column i/o write driver sense amp column decoder address input buffer a 4 a 3 a 2 a 1 a0 data input buffer control dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 a7 a12 a14 a16 a17 a15 a11 a8 a9 a13 8 8 8 8 8 256 2048 1024 10 a 10 a 6 ce2 ce1 we oe v cc gnd data output buffer a5 g h f e d c b a 1 2 3 4 5 6 a11 a13 a12 a14 ce1 nc a16 a17 a15 dq3 dq2 vss vcc nc a1 we ce2 a5 a4 a3 a6 a8 a2 a7 dq1 dq0 36-ball bga top view a0 dq4 dq5 vss vcc dq6 dq7 a9 oe a10
b s 6 2l v 2006 r0201-bs62lv2006 revision 1.3 may. 2006 2 n pin descriptions name function a0-a17 address input these 18 address inputs select one of the 262,144 x 8-bit in the ram ce1 chip enable 1 input ce2 chip enable 2 input ce1 is active low and ce2 is active high. both chip enables must be active when data read form or write to the device. if either chip enable is not active, the device is deselected and is in standby power mode. the dq pins will be in the high impedance state when the device is deselected. we write enable input the write enable input is active low and controls read and write operations . with the chip selected, when we is high and oe is low, output data will be present on the dq pins; when we is low, the data present on the dq pins will be written into the selected memory location. oe output enable input the output enable input is active low. if the output enable is active while the chip is selected and the write enable is inactive, data will be present on the dq pins and they will be enabled. the dq pins will be in the high impendence state when oe is inactive. dq0-dq7 data input/output ports there 8 bi-directional ports are used to read data from or write data into the ram. v cc power supply gnd ground n truth table mode ce1 ce2 we oe i/o operation v cc current h x x x not selected (power down) x l x x high z i ccsb , i ccsb1 output disabled l h h h high z i cc read l h h l d out i cc write l h l x d in i cc n absolute maximum ratings (1) symbol parameter rating units v term terminal voltage with respect to gnd -0.5 (2) to 7.0 v t bias temperature under bias -40 to +125 o c t stg storage temperature -60 to +150 o c p t power dissipation 1.0 w i out dc output current 20 ma 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. C 2.0v in case of ac pulse width less than 30 ns. n operating range rang ambient temperature v cc commercial 0 o c to + 70 o c 2.4v ~ 5.5v industrial -40 o c to + 85 o c 2.4v ~ 5.5v n capacitance (1) (t a = 25 o c, f = 1.0mhz) symbol pamameter conditions max. units c in input capacitance v in = 0v 6 pf c io input/output capacitance v i/o = 0v 8 pf 1. this parameter is guaranteed and not 100% tested.
b s 6 2l v 2006 r0201-bs62lv2006 revision 1.3 may. 2006 3 n dc electrical characteristics (t a = -40 o c to +85 o c) parameter name parameter test conditions min. typ. (1) max. units v cc power supply 2.4 -- 5.5 v v il input low voltage -0.5 (2) -- 0.8 v v ih input high voltage 2.2 -- v cc +0.3 (3) v i il input leakage current v cc = max, v in = 0v to v cc -- -- 1 ua i lo output leakage current v cc = max, ce1= v ih , ce2= v il , or oe = v ih , v i/o = 0v to v cc -- -- 1 ua v ol output low voltage v cc = max, i ol = 2.0ma -- -- 0.4 v v oh output high voltage v cc = min, i oh = -1.0ma 2.4 -- -- v v cc =3.0v -- -- 23 i cc (5) operating power supply current ce1 = v il , ce2 = v ih , i dq = 0ma, f = f max (4) v cc =5.0v -- -- 55 ma v cc =3.0v -- -- 2 i cc1 operating power supply current ce1 = v il , ce2 = v ih , i dq = 0ma, f = 1mhz v cc =5.0v -- -- 10 ma v cc =3.0v -- -- 0.5 i ccsb standby current C ttl ce1 = v ih , or ce2 = v il , i dq = 0ma v cc =5.0v -- -- 1.0 ma v cc =3.0v -- 0.1 2.0 i ccsb1 (6) standby current C cmos ce1 R v cc -0.2v or ce2 Q 0.2v, v in R v cc -0.2v or v in Q 0.2v v cc =5.0v -- 0.6 20 ua 1. typical characteristics are at t a =25 o c and not 100% tested. 2. undershoot: -1.0v in case of pulse width less than 20 ns. 3. overshoot: v cc +1.0v in case of pulse width less than 20 ns. 4. f max =1/t rc. 5. i cc (max.) is 22ma/53ma at v cc =3.0v/5.0v and t a =70 o c. 6. i ccsb1(max.) is 0.7ua/6.0ua at v cc =3.0v/5.0v and t a =70 o c. n data retention characteristics (t a = -40 o c to +85 o c) symbol parameter test conditions min. typ. (1) max. units v dr v cc for data retention ce1 R v cc -0.2v or ce2 Q 0.2v, v in R v cc -0.2v or v in Q 0.2v 1.5 -- -- v i ccdr (3) data retention current ce1 R v cc -0.2v or ce2 Q 0.2v, v in R v cc -0.2v or v in Q 0.2v -- 0.05 1.0 ua t cdr chip deselect to data retention time 0 -- -- ns t r operation recovery time see retention waveform t rc (2) -- -- ns 1. v cc =1.5v, t a =25 o c and not 100% tested. 2. t rc = read cycle time. 3. i ccrd(max.) is 0.5ua at t a =70 o c. n low v cc data retention waveform (1) (ce1 controlled) data retention mode v cc t cdr v cc t r v ih v ih ce1 R v cc - 0.2v v dr R 1.5v ce1 v cc
b s 6 2l v 2006 r0201-bs62lv2006 revision 1.3 may. 2006 4 n low v cc data retention waveform (2) (ce2 controlled) n ac test conditions (test load and input/output reference) input pulse levels vcc / 0v input rise and fall times 1v/ns input and output timing reference level 0.5vcc t clz , t olz , t chz , t ohz , t whz c l = 5pf+1ttl output load others c l = 30pf+1ttl 1. including jig and scope capacitance. n key to switching waveforms waveform inputs outputs must be steady must be steady may change from h to l will be change from h to l may change from l to h will be change from l to h don t care any change permitted change : state unknow does not apply center line is high inpedance off state n ac electrical characteristics (t a = -40 o c to +85 o c) read cycle cycle time : 55ns (v cc = 3.0~5.5v) cycle time : 70ns (v cc = 2.7~5.5v) jedec parameter name paraneter name description min. typ. max. min. typ. max. units t avax t rc read cycle time 55 -- -- 70 -- -- ns t avqx t aa address access time -- -- 55 -- -- 70 ns t e1lqv t acs1 chip select access time (ce1) -- -- 55 -- -- 70 ns t e2hqv t acs2 chip select access time (ce2) -- -- 55 -- -- 70 ns t glqv t oe output enable to output valid -- -- 30 -- -- 35 ns t e1lqx t clz1 chip select to output low z (ce1) 10 -- -- 10 -- -- ns t e2hqx t clz2 chip select to output low z (ce2) 10 -- -- 10 -- -- ns t glqx t olz output enable to output low z 5 -- -- 5 -- -- ns t e1hqz t chz1 chip select to output high z (ce1) -- -- 30 -- -- 35 ns t e2lqz t chz2 chip select to output high z (ce2) -- -- 30 -- -- 35 ns t ghqz t ohz output enable to output high z -- -- 25 -- -- 30 ns t avqx t oh data hold from address change 10 -- -- 10 -- -- ns ce2 data retention mode v cc t cdr v cc t r v il v il v cc v dr R 1.5v ce2 Q 0.2v c l (1) 1 ttl output all input pulses ? ? 90% v cc gnd rise time : 1v/ns fall time : 1v/ns 90% ? ? 10% 10%
b s 6 2l v 2006 r0201-bs62lv2006 revision 1.3 may. 2006 5 n switching waveforms (read cycle) read cycle 1 (1,2,4) read cycle 2 (1,3,4) read cycle 3 (1, 4) notes: 1. we is high in read cycle. 2. device is continuously selected when ce1 = v il and ce2= v ih . 3. address valid prior to or coincident with ce1 transition low and/or ce2 transition high. 4. oe = v il . 5. transition is measured 500mv from steady state with c l = 5pf. the parameter is guaranteed but not 100% tested. t rc t oh t aa d out address t oh t clz (5) d out ce2 ce1 t acs2 t acs1 t chz1 , t chz2 (5) t oh t rc t oe t clz2 (5) t chz2 (2,5) d out ce2 ce1 oe address t clz1 (5) t acs1 t acs2 t chz1 (1,5) t ohz (5) t olz t aa
b s 6 2l v 2006 r0201-bs62lv2006 revision 1.3 may. 2006 6 n ac electrical characteristics (t a = -40 o c to +85 o c) write cycle cycle time : 55ns (v cc = 3.0~5.5v) cycle time : 70ns (v cc = 2.7~5.5v) jedec parameter name paraneter name description min. typ. max. min. typ. max. units t avax t wc write cycle time 55 -- -- 70 -- -- ns t e1lwh t cw chip select to end of write 55 -- -- 70 -- -- ns t avwl t as address set up time 0 -- -- 0 -- -- ns t avwh t aw address valid to end of write 55 -- -- 70 -- -- ns t wlwh t wp write pulse width 30 -- -- 35 -- -- ns t whax t wr1 write recovery time (ce1, we) 0 -- -- 0 -- -- ns t e2lax t wr2 write recovery time (ce2) 0 -- -- 0 -- -- ns t wlqz t whz write to output high z -- -- 25 -- -- 30 ns t dvwh t dw data to write time overlap 25 -- -- 30 -- -- ns t whdx t dh data hold from write time 0 -- -- 0 -- -- ns t ghqz t ohz output disable to output in high z -- -- 25 -- -- 30 ns t whqx t ow end of write to output active 5 -- -- 5 -- -- ns n switching waveforms (write cycle) write cycle 1 (1) t wc t wr1 (3) t cw (11) t cw (11) t wp (2) t aw t ohz (4,10) t as t wr2 (3) t dh t dw d in d out we ce2 ce1 oe address (5) (5)
b s 6 2l v 2006 r0201-bs62lv2006 revision 1.3 may. 2006 7 write cycle 2 (1,6) notes: 1. we must be high during address transitions. 2. the internal write time of the memory is defined by the overlap of ce1 and ce2 active and we low. all signals must be active to initiate a write and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t wr is measured from the earlier of ce1 or we going high or ce2 going low at the end of write cycle. 4. during this period, dq pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. if the ce1 low transition or the ce2 high transition occurs simultaneously with the we low transitions or after the we transition, output remain in a high impedance state. 6. oe is continuously low (oe = v il ). 7. d out is the same phase of write data of this write cycle. 8. d out is the read data of next address. 9. if ce1 is low and ce2 is high during this period, dq pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 10. transition is measured 500mv from steady state with c l = 5pf. the parameter is guaranteed but not 100% tested. 11. t cw is measured from the later of ce1 going low or ce2 going high to the end of write. t wc t cw (11) t cw (11) t wp (2) t aw t whz (4,10) t as t wr2 (3) t dh t dw d in d out we ce2 ce1 address (5) (5) t ow (7) (8) (8,9)
b s 6 2l v 2006 r0201-bs62lv2006 revision 1.3 may. 2006 8 n ordering information note: bsi (brilliance semiconductor inc.) assumes no responsibility for the application or use of any product or circuit described herein. bsi does not authorize its products for use as critical components in any application in which the failure of the bsi product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. n package dimensions package d: dice h: bga-36-0608 s: sop t: tsop (8mm x 20mm) st: small tsop (8mm x 13.4mm) bs62lv2006 x x z y y grade c: +0 o c ~ +70 o c i: -40 o c ~ +85 o c spee d 55: 55ns 70 : 70 ns pkg material -: normal g: green, rohs compliant p: pb free, rohs compliant base metal with plating c c1 section a-a b1 b sop -32
b s 6 2l v 2006 r0201-bs62lv2006 revision 1.3 may. 2006 9 n package dimensions (continued) n stsop - 32 tsop - 32
b s 6 2l v 2006 r0201-bs62lv2006 revision 1.3 may. 2006 10 package dimensions (continued) 36 mini-bga (6 x 8mm) d1 view a 1 . 2 m a x . e e 1 1: controlling dimensions are in millimeters. 2: pin#1 dot marking by laser or pad print. 3: symbol "n" is the number of solder balls. ball pitch e = 0.75 d 8.0 6.0 e n 48 3.75 e1 d1 5.25 notes :
b s 6 2l v 2006 r0201-bs62lv2006 revision 1.3 may. 2006 11 n revision history revision no. history draft date remark 1.2 add icc1 characteristic parameter jan. 13, 2006 improve iccsb1 spec. i-grade from 30ua to 20ua at 5.0v 5.0ua to 2.0ua at 3.0v c-grade from 10ua to 6.0ua at 5.0v 3.0ua to 0.7ua at 3.0v 1.3 change i-grade operation temperature range may. 25, 2006 - from C 25 o c to C 40 o c

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